PIC18F4580ISOSQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F4580ISOSQTP
Microchip Technology
PIC18F4580ISOSQTP Datasheet PDF : 490 Pages
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PIC18F2480/2580/4480/4580
REGISTER 24-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE
[0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1](1)
R/W-0
TXBIF(3)
bit 7
R-0
TXABT(3)
R-0
TXLARB(3)
R-0
R/W-0
TXERR(3) TXREQ(2,4)
R/W-0
RTREN
R/W-0
TXPRI1(5)
R/W-0
TXPRI0(5)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
TXBIF: Transmit Buffer Interrupt Flag bit(3)
1 = A message is successfully transmitted
0 = No message was transmitted
TXABT: Transmission Aborted Status bit(3)
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit(3)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit(3)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit(2,4)
1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits
0 = Automatically cleared when the message is successfully sent
RTREN: Automatic Remote Transmission Request Enable bit
1 = When a remote transmission request is received, TXREQ will be automatically set
0 = When a remote transmission request is received, TXREQ will be unaffected
TXPRI<1:0>: Transmit Priority bits(5)
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
Note 1:
2:
3:
4:
5:
These registers are available in Mode 1 and 2 only.
Clearing this bit in software while the bit is set will request a message abort.
This bit is automatically cleared when TXREQ is set.
While TXREQ is set or a transmission is in progress, Transmit Buffer registers remain read-only.
These bits set the order in which the Transmit Buffer register will be transferred. They do not alter the CAN
message identifier.
© 2009 Microchip Technology Inc.
DS39637D-page 301
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