PIC18F4580ISOSQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F4580ISOSQTP
Microchip Technology
PIC18F4580ISOSQTP Datasheet PDF : 490 Pages
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PIC18F2480/2580/4480/4580
ADDWF
ADD W to Indexed
(Indexed Literal Offset mode)
Syntax:
ADDWF [k] {,d}
Operands:
0 ≤ k ≤ 95
d ∈ [0,1]
a=0
Operation:
(W) + ((FSR2) + k) → dest
Status Affected: N, OV, C, DC, Z
Encoding:
0010 01d0 kkkk kkkk
Description:
The contents of W are added to the contents
of the register indicated by FSR2, offset by the
value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read ‘k’
Q3
Process
Data
Q4
Write to
destination
Example:
ADDWF [OFST] ,0
Before Instruction
W
OFST
FSR2
Contents
of 0A2Ch
After Instruction
W
Contents
of 0A2Ch
= 17h
= 2Ch
= 0A00h
= 20h
= 37h
= 20h
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Set Indexed
(Indexed Literal Offset mode)
BSF [k], b
0 ≤ f ≤ 95
0≤b≤7
a=0
1 → ((FSR2 + k))<b>
None
1000 bbb0 kkkk kkkk
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
BSF
Before Instruction
FLAG_OFST
FSR2
Contents
of 0A0Ah
After Instruction
Contents
of 0A0Ah
[FLAG_OFST], 7
= 0Ah
= 0A00h
= 55h
= D5h
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Set Indexed
(Indexed Literal Offset mode)
SETF [k]
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
0110 1000 kkkk kkkk
The contents of the register indicated
by FSR2, offset by ‘k’, are set to FFh.
1
1
Q2
Read ‘k’
Q3
Process
Data
Q4
Write
register
Example:
SETF
Before Instruction
OFST
=
FSR2
=
Contents
of 0A2Ch
=
After Instruction
Contents
of 0A2Ch
=
[OFST]
2Ch
0A00h
00h
FFh
© 2009 Microchip Technology Inc.
DS39637D-page 415
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