PIC18LF25800TESOSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF25800TESOSQTP

28/40/44-Pin Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F2480/2580/4480/4580

5.0 RESET

The PIC18F2480/2580/4480/4580 devices differentiate

between various kinds of Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during power-managed modes

d) Watchdog Timer (WDT) Reset (during

execution)

e) Programmable Brown-out Reset (BOR)

f) RESET Instruction

g) Stack Full Reset

h) Stack Underflow Reset

This section discusses Resets generated by MCLR,

POR and BOR, and covers the operation of the various

start-up timers. Stack Reset events are covered in

Section 6.1.2.4 “Stack Full and Underflow Resets”.

WDT Resets are covered in Section 25.2 “Watchdog

Timer (WDT)”.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 5-1.

5.1 RCON Register

Device Reset events are tracked through the RCON

register (Register 5-1). The lower five bits of the regis-

ter indicate that a specific Reset event has occurred. In

most cases, these bits can only be cleared by the event

and must be set by the application after the event. The

state of these flag bits, taken together, can be read to

indicate the type of Reset that just occurred. This is

described in more detail in Section 5.6 “Reset State

of Registers”.

The RCON register also has control bits for setting

interrupt priority (IPEN) and software control of the

BOR (SBOREN). Interrupt priority is discussed in

Section 10.0 “Interrupts”. BOR is covered in

Section 5.4 “Brown-out Reset (BOR)”.

FIGURE 5-1:

RESET

Instruction

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Stack Stack Full/Underflow Reset

Pointer

External Reset

MCLR

MCLRE

( )_IDLE

Sleep

WDT

Time-out

VDD Rise POR Pulse

Detect

VDD

Brown-out

Reset

BOREN

S

OSC1

OST/PWRT

OST

1024 Cycles

10-Bit Ripple Counter

Chip_Reset

R

Q

32 μs

INTRC(1)

PWRT 65.5 ms

11-Bit Ripple Counter

Enable PWRT

Enable OST(2)

Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.

2: See Table 5-2 for time-out situations.

© 2009 Microchip Technology Inc.

DS39637D-page 47

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