PIC18F44J10T-I/ML(2009) View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F44J10T-I/ML
(Rev.:2009)

28/40/44-Pin High-Performance, RISC Microcontrollers

Microchip Technology 

PIC18F45J10 FAMILY

22.1.1 STANDARD INSTRUCTION SET

ADDLW

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

ADD Literal to W

ADDLW k

0 ≤ k ≤ 255

(W) + k → W

N, OV, C, DC, Z

0000 1111 kkkk kkkk

The contents of W are added to the

8-bit literal ‘k’ and the result is placed in

W.

1

1

Q2

Read

literal ‘k’

Q3

Process

Data

Q4

Write to W

Example:

ADDLW 15h

Before Instruction

W = 10h

After Instruction

W = 25h

ADDWF

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

ADD W to f

ADDWF f {,d {,a}}

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) + (f) → dest

N, OV, C, DC, Z

0010 01da ffff ffff

Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

1

Q Cycle Activity:

Q1

Decode

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write to

destination

Example:

ADDWF

Before Instruction

W

=

REG =

After Instruction

17h

0C2h

W

REG

= 0D9h

= 0C2h

REG, 0, 0

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

© 2009 Microchip Technology Inc.

DS39682E-page 255

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