PIC18F44J10T-I/ML(2009) View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F44J10T-I/ML
(Rev.:2009)

28/40/44-Pin High-Performance, RISC Microcontrollers

Microchip Technology 

PIC18F45J10 FAMILY

BRA

Unconditional Branch

Syntax:

BRA n

Operands:

-1024 ≤ n ≤ 1023

Operation:

(PC) + 2 + 2n → PC

Status Affected: None

Encoding:

1101 0nnn nnnn nnnn

Description:

Add the 2’s complement number, ‘2n’, to

the PC. Since the PC will have

incremented to fetch the next instruction,

the new address will be PC + 2 + 2n. This

instruction is a two-cycle instruction.

Words:

1

Cycles:

2

Q Cycle Activity:

Q1

Decode

No

operation

Q2

Read literal

‘n’

No

operation

Q3

Process

Data

No

operation

Q4

Write to PC

No

operation

Example:

HERE

Before Instruction

PC

=

After Instruction

PC

=

BRA Jump

address (HERE)

address (Jump)

BSF

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

Bit Set f

BSF f, b {,a}

0 ≤ f ≤ 255

0≤b≤7

a ∈ [0,1]

1 → f<b>

None

1000 bbba ffff ffff

Bit ‘b’ in register ‘f’ is set.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 22.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write

register ‘f’

Example:

BSF

Before Instruction

FLAG_REG =

After Instruction

FLAG_REG =

FLAG_REG, 7, 1

0Ah

8Ah

© 2009 Microchip Technology Inc.

DS39682E-page 261

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