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PIC18LF45J10T-I/SP View Datasheet(PDF) - Microchip Technology

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PIC18LF45J10T-I/SP Datasheet PDF : 358 Pages
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PIC18F45J10 FAMILY
FIGURE 14-2:
PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
CCP1CON
<7:6>
SIGNAL
0
Duty
Cycle
Period
00 (Single Output)
10 (Half-Bridge)
(Full-Bridge,
01 Forward)
(Full-Bridge,
11
Reverse)
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Delay(1)
Delay(1)
PR2 + 1
FIGURE 14-3:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
CCP1CON
<7:6>
SIGNAL
0
Duty
Cycle
Period
PR2 + 1
00 (Single Output)
10 (Half-Bridge)
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
Delay(1)
Delay(1)
(Full-Bridge,
01 Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
(Full-Bridge,
11
Reverse)
P1B Modulated
P1C Active
P1D Inactive
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 14.4.6 “Programmable
Dead-Band Delay”).
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 135

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