PIC18LF45J10T-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF45J10T-I/SP

28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F45J10 FAMILY

NEGF

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

Negate f

NEGF f {,a}

0 ≤ f ≤ 255

a ∈ [0,1]

(f)+1→f

N, OV, C, DC, Z

0110 110a ffff ffff

Location ‘f’ is negated using two’s

complement. The result is placed in the

data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write

register ‘f’

Example:

NEGF REG, 1

Before Instruction

REG =

After Instruction

REG =

0011 1010 [3Ah]

1100 0110 [C6h]

NOP

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

No Operation

NOP

None

No operation

None

0000 0000

1111 xxxx

No operation.

1

1

0000

xxxx

0000

xxxx

Q2

No

operation

Q3

No

operation

Q4

No

operation

Example:

None.

© 2007 Microchip Technology Inc.

Preliminary

DS39682C-page 269

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