PIC18F25J10T-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F25J10T-I/SO

28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F45J10 FAMILY

SUBLW

Subtract W from Literal

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

SUBLW k

0 ≤ k ≤ 255

k – (W) → W

N, OV, C, DC, Z

0000 1000 kkkk kkkk

W is subtracted from the eight-bit

literal ‘k’. The result is placed in W.

1

1

Q2

Read

literal ‘k’

Q3

Process

Data

Q4

Write to W

Example 1:

SUBLW 02h

Before Instruction

W

=

C

=

After Instruction

W

=

C

=

Z

=

N

=

01h

?

01h

1 ; result is positive

0

0

Example 2:

SUBLW 02h

Before Instruction

W

=

C

=

After Instruction

W

=

C

=

Z

=

N

=

02h

?

00h

1 ; result is zero

1

0

Example 3:

SUBLW 02h

Before Instruction

W

=

C

=

After Instruction

W

=

C

=

Z

=

N

=

03h

?

FFh ; (2’s complement)

0 ; result is negative

0

1

SUBWF

Subtract W from f

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

SUBWF f {,d {,a}}

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(f) – (W) → dest

N, OV, C, DC, Z

0101 11da ffff ffff

Subtract W from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 21.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write to

destination

Example 1:

SUBWF REG, 1, 0

Before Instruction

REG

W

C

=3

=2

=?

After Instruction

REG

W

C

Z

N

=1

=2

=1

=0

=0

; result is positive

Example 2:

SUBWF REG, 0, 0

Before Instruction

REG = 2

W

=2

C

=?

After Instruction

REG = 2

W

=0

C

=1

Z

=1

N

=0

; result is zero

Example 3:

SUBWF REG, 1, 0

Before Instruction

REG =

W

=

C

=

After Instruction

REG =

W

=

C

=

Z

=

N

=

1

2

?

FFh ;(2’s complement)

2

0 ; result is negative

0

1

© 2007 Microchip Technology Inc.

Preliminary

DS39682C-page 277

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