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PIC18LF45J10-I/SP View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC18LF45J10-I/SP Datasheet PDF : 358 Pages
First Prev 341 342 343 344 345 346 347 348 349 350 Next Last
PIC18F45J10 FAMILY
Enhanced PWM Mode. See PWM (ECCP Module).......... 133
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
Equations
A/D Acquisition Time................................................. 214
A/D Minimum Charging Time.................................... 214
Errata .................................................................................... 6
EUSART
Asynchronous Mode ................................................. 197
12-Bit Break Transmit and Receive .................. 202
Associated Registers, Receive ......................... 200
Associated Registers, Transmit ........................ 198
Auto-Wake-up on Sync Break .......................... 200
Receiver............................................................ 199
Setting Up 9-Bit Mode with Address Detect...... 199
Transmitter........................................................ 197
Baud Rate Generator
Operation in Power-Managed Mode ................. 191
Baud Rate Generator (BRG)..................................... 191
Associated Registers ........................................ 192
Auto-Baud Rate Detect ..................................... 195
Baud Rate Error, Calculating ............................ 192
Baud Rates, Asynchronous Modes .................. 193
High Baud Rate Select (BRGH Bit) .................. 191
Sampling ........................................................... 191
Synchronous Master Mode ....................................... 203
Associated Registers, Receive ......................... 205
Associated Registers, Transmit ........................ 204
Reception.......................................................... 205
Transmission .................................................... 203
Synchronous Slave Mode ......................................... 206
Associated Registers, Receive ......................... 207
Associated Registers, Transmit ........................ 206
Reception.......................................................... 207
Transmission .................................................... 206
Extended Instruction Set
ADDFSR ................................................................... 284
ADDULNK................................................................. 284
and Using MPLAB Tools........................................... 290
CALLW...................................................................... 285
Considerations for Use ............................................. 288
MOVSF ..................................................................... 285
MOVSS ..................................................................... 286
PUSHL ...................................................................... 286
SUBFSR ................................................................... 287
SUBULNK ................................................................. 287
Syntax ....................................................................... 283
External Clock Input (EC Modes)........................................ 24
F
Fail-Safe Clock Monitor............................................. 229, 238
Interrupts in Power-Managed Modes........................ 239
POR or Wake-up from Sleep .................................... 239
WDT During Oscillator Failure .................................. 238
Fast Register Stack............................................................. 50
Firmware Instructions........................................................ 241
Flash Configuration Words ............................................... 229
Flash Program Memory ...................................................... 67
Associated Registers .................................................. 75
Control Registers ........................................................ 68
EECON1 and EECON2 ...................................... 68
TABLAT (Table Latch) ........................................ 70
TBLPTR (Table Pointer) ..................................... 70
Erase Sequence ......................................................... 72
Erasing........................................................................ 72
Operation During Code-Protect .................................. 75
Reading ...................................................................... 71
Table Pointer
Boundaries Based on Operation ........................ 70
Table Pointer Boundaries ........................................... 70
Table Reads and Table Writes ................................... 67
Write Sequence .......................................................... 73
Writing To ................................................................... 73
Protection Against Spurious Writes .................... 75
Unexpected Termination .................................... 75
Write Verify ......................................................... 75
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 262
H
Hardware Multiplier............................................................. 77
Introduction................................................................. 77
Operation.................................................................... 77
Performance Comparison........................................... 77
I
I/O Ports ............................................................................. 93
I2C Mode (MSSP)
Acknowledge Sequence Timing ............................... 179
Associated Registers................................................ 185
Baud Rate Generator ............................................... 172
Bus Collision
During a Repeated Start Condition................... 183
During a Stop Condition ................................... 184
Clock Arbitration ....................................................... 173
Clock Stretching ....................................................... 165
10-Bit Slave Receive Mode (SEN = 1) ............. 165
10-Bit Slave Transmit Mode ............................. 165
7-Bit Slave Receive Mode (SEN = 1) ............... 165
7-Bit Slave Transmit Mode ............................... 165
Clock Synchronization and the CKP Bit ................... 166
Effects of a Reset ..................................................... 180
General Call Address Support .................................. 169
I2C Clock Rate w/BRG ............................................. 172
Master Mode............................................................. 170
Baud Rate Generator ....................................... 172
Operation.......................................................... 171
Reception ......................................................... 176
Repeated Start Condition Timing ..................... 175
Start Condition Timing ...................................... 174
Transmission .................................................... 176
Multi-Master Communication, Bus Collision and
Arbitration ......................................................... 180
Multi-Master Mode.................................................... 180
Operation.................................................................. 159
Read/Write Bit Information (R/W Bit)................ 159, 160
Registers .................................................................. 155
Serial Clock (SCKx/SCLx) ........................................ 160
Slave Mode............................................................... 159
Addressing ....................................................... 159
Reception ......................................................... 160
Transmission .................................................... 160
Sleep Operation........................................................ 180
Stop Condition Timing .............................................. 179
INCF ................................................................................. 262
INCFSZ............................................................................. 263
In-Circuit Debugger........................................................... 240
In-Circuit Serial Programming (ICSP)....................... 229, 240
Indexed Literal Offset Addressing
and Standard PIC18 Instructions.............................. 288
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 345

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