PIC18LF45J10-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF45J10-I/SP

28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F45J10 FAMILY

4.5 Power-up Timer (PWRT)

PIC18F45J10 family devices incorporate an on-chip

Power-up Timer (PWRT) to help regulate the Power-on

Reset process. The PWRT is always enabled. The

main function is to ensure that the device voltage is

stable before code is executed.

The Power-up Timer (PWRT) of the PIC18F45J10

family devices is an 11-bit counter which uses the

INTRC source as the clock input. This yields an

approximate time interval of 2048 x 32 μs = 65.6 ms.

While the PWRT is counting, the device is held in

Reset.

The power-up time delay depends on the INTRC clock

and will vary from chip to chip due to temperature and

process variation. See DC parameter 33 for details.

4.5.1 TIME-OUT SEQUENCE

If enabled, the PWRT time-out is invoked after the POR

pulse has cleared. The total time-out will vary based on

the status of the PWRT. Figure 4-3, Figure 4-4,

Figure 4-5 and Figure 4-6 all depict time-out

sequences on power-up with the Power-up Timer

enabled.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the PWRT will expire. Bringing

MCLR high will begin execution immediately

(Figure 4-5). This is useful for testing purposes, or to

synchronize more than one PIC18F device operating in

parallel.

FIGURE 4-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

TPWRT

FIGURE 4-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

TPWRT

DS39682C-page 40

Preliminary

© 2007 Microchip Technology Inc.

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