PIC18F45J50-I/SOSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F45J50-I/SOSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

9.1 INTCON Registers

The INTCON registers are readable and writable

registers, which contain various enable, priority and

flag bits.

Note:

Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

This feature allows for software polling.

REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER (ACCESS FF2h)

R/W-0

GIE/GIEH

bit 7

R/W-0

PEIE/GIEL

R/W-0

TMR0IE

R/W-0

INT0IE

R/W-0

RBIE

R/W-0

TMR0IF

R/W-0

INT0IF

R/W-x

RBIF(1)

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked interrupts

0 = Disables all interrupts

When IPEN = 1:

1 = Enables all high-priority interrupts (also enables low-priority interrupts when GIEL is also set)

0 = Disables all interrupts

bit 6

PEIE/GIEL: Peripheral/Low-Priority Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked peripheral interrupts (when GIE is also set)

0 = Disables all peripheral interrupts

When IPEN = 1:

1 = Enables all interrupts configured for low priority (when GIEH is also set)

0 = Disables all interrupts configured for low priority

bit 5

TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt

0 = Disables the TMR0 overflow interrupt

bit 4

INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt

0 = Disables the INT0 external interrupt

bit 3

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2

TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1

INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software)

0 = The INT0 external interrupt did not occur

bit 0

RBIF: RB Port Change Interrupt Flag bit(1)

1 = At least one of the RB<7:4> pins changed state (must be cleared in software)

0 = None of the RB<7:4> pins have changed state

Note 1: A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 TCY will end the mismatch

condition and allow the bit to be cleared.

 2011 Microchip Technology Inc.

DS39931D-page 117

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