PIC18F44J50-I/SPSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F44J50-I/SPSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h)

R/W-1

RBPU

bit 7

R/W-1

INTEDG0

R/W-1

INTEDG1

R/W-1

INTEDG2

R/W-1

INTEDG3

R/W-1

TMR0IP

R/W-1

INT3IP

R/W-1

RBIP

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual PORT TRIS values

bit 6

INTEDG0: External Interrupt 0 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 5

INTEDG1: External Interrupt 1 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 4

INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 3

INTEDG3: External Interrupt 3 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 2

TMR0IP: TMR0 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1

INT3IP: INT3 External Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0

RBIP: RB Port Change Interrupt Priority bit

1 = High priority

0 = Low priority

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding

enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt. This feature allows for software polling.

DS39931D-page 118

 2011 Microchip Technology Inc.

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