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PIC18F26J50-I/SPQTP View Datasheet(PDF) - Microchip Technology

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PIC18F26J50-I/SPQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
10.7.6
PERIPHERAL PIN SELECT
REGISTERS
The PIC18F46J50 family of devices implements a total
of 37 registers for remappable peripheral configuration
of 44-pin devices. The 28-pin devices have 31 registers
for remappable peripheral configuration.
Note:
Input and output register values can only
be changed if IOLOCK (PPSCON<0>) = 0.
See Example 10-7 for a specific command
sequence.
REGISTER 10-6: PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED EFFh)(1)
U-0
bit 7
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
IOLOCK
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
bit 0
Unimplemented: Read as ‘0
IOLOCK: I/O Lock Enable bit
1 = I/O lock is active, RPORx and RPINRx registers are write-protected
0 = I/O lock is not active, pin configurations can be changed
Note 1: Register values can only be changed if IOLOCK (PPSCON<0>) = 0.
2011 Microchip Technology Inc.
DS39931D-page 155

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