PIC18F45J50-I/SOSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F45J50-I/SOSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

11.1 Module Registers

The PMP module has a total of 14 Special Function

Registers (SFRs) for its operation, plus one additional

register to set configuration options. Of these, eight

registers are used for control and six are used for PMP

data transfer.

11.1.1 CONTROL REGISTERS

The eight PMP Control registers are:

• PMCONH and PMCONL

• PMMODEH and PMMODEL

• PMSTATL and PMSTATH

• PMEH and PMEL

The PMCON registers (Register 11-1 and

Register 11-2) control basic module operations, includ-

ing turning the module on or off. They also configure

address multiplexing and control strobe configuration.

The PMMODE registers (Register 11-3 and

Register 11-4) configure the various Master and Slave

modes, the data width and interrupt generation.

The PMEH and PMEL registers (Register 11-5 and

Register 11-6) configure the module’s operation at the

hardware (I/O pin) level.

The PMSTAT registers (Register 11-5 and

Register 11-6) provide status flags for the module’s

input and output buffers, depending on the operating

mode.

REGISTER 11-1: PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE (BANKED F5Fh)(1)

R/W-0

U-0

PMPEN

—

bit 7

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

—

ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6-5

bit 4-3

bit 2

bit 1

bit 0

PMPEN: Parallel Master Port Enable bit

1 = PMP is enabled

0 = PMP is disabled, no off-chip access is performed

Unimplemented: Read as ‘0’

ADRMUX<1:0>: Address/Data Multiplexing Selection bits

11 = Reserved

10 = All 16 bits of the address are multiplexed on PMD<7:0> pins

01 = Lower 8 bits of the address are multiplexed on PMD<7:0> pins (only eight bits of address are

available in this mode)

00 = Address and data appear on separate pins (only eight bits of address are available in this mode)

PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)

1 = PMBE port is enabled

0 = PMBE port is disabled

PTWREN: Write Enable Strobe Port Enable bit

1 = PMWR/PMENB port is enabled

0 = PMWR/PMENB port is disabled

PTRDEN: Read/Write Strobe Port Enable bit

1 = PMRD/PMWR port is enabled

0 = PMRD/PMWR port is disabled

Note 1: This register is only available on 44-pin devices.

DS39931D-page 170

 2011 Microchip Technology Inc.

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