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PIC18F44J50-I/SPSQTP View Datasheet(PDF) - Microchip Technology

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PIC18F44J50-I/SPSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
24.1 Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 24-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels. The range
to be used is selected by the CVRR bit (CVRCON<5>).
The primary difference between the ranges is the size
of the steps selected by the CVREF Selection bits
(CVR<3:0>), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:
EQUATION 24-1: CALCULATING OUTPUT
OF THE COMPARATOR
VOLTAGE REFERENCE
When CVRR = 1:
CVREF = ((CVR<3:0>)/24) x (VDD)
When CVRR = 0:
CVREF = (VDD/4) + ((CVR<3:0>)/32) x (VDD)
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 30-3 in Section 30.0 “Electrical
Characteristics”).
REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
(BANKED F53h)
R/W-0
CVREN
bit 7
R/W-0
CVROE(1)
R/W-0
CVRR
R/W-0
r
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit is powered on
0 = CVREF circuit is powered down
CVROE: Comparator VREF Output Enable bit(1)
1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2INB pin
0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2INB pin
CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 VDD, with VDD/24 step size (low range)
0 = 0.25 VDD to 0.75 VDD, with VDD/32 step size (high range)
Reserved: Always maintain as ‘0
CVR<3:0>: Comparator VREF Value Selection bits (0 (CVR<3:0>) 15)
When CVRR = 1:
CVREF = ((CVR<3:0>)/24) (VDD)
When CVRR = 0:
CVREF = (VDD/4) + ((CVR<3:0>)/32) (VDD)
Note 1: CVROE overrides the TRIS bit setting.
DS39931D-page 392
2011 Microchip Technology Inc.

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