PIC18F45J50-I/SOSQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F45J50-I/SOSQTP
Microchip Technology
PIC18F45J50-I/SOSQTP Datasheet PDF : 562 Pages
| |||
PIC18F46J50 FAMILY
ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
AND W with f
ANDWF f {,d {,a}}
0 f 255
d [0,1]
a [0,1]
(W) .AND. (f) dest
N, Z
0001 01da ffff ffff
The contents of W are ANDed with
register, ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 28.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
ANDWF
Before Instruction
W
REG
= 17h
= C2h
After Instruction
W
REG
= 02h
= C2h
REG, 0, 0
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
Branch if Carry
BC n
-128 n 127
if Carry bit is ‘1’,
(PC) + 2 + 2n PC
None
1110 0010 nnnn nnnn
If the Carry bit is ’1’, then the program
will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
‘n’
No
operation
Q3
Process
Data
No
operation
Q4
Write to
PC
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Carry
=
PC
=
If Carry
=
PC
=
BC 5
address (HERE)
1;
address (HERE + 12)
0;
address (HERE + 2)
2011 Microchip Technology Inc.
DS39931D-page 443
Share Link: 