PIC18F45J50-I/SOSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F45J50-I/SOSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

FIGURE 30-7:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

VDD

MCLR

Internal

POR

PWRT

Time-out

Oscillator

Time-out

Internal

Reset

Watchdog

Timer

Reset

I/O pins

33

32

30

34

31

34

Note: Refer to Figure 30-4 for load conditions.

TABLE 30-14: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min Typ Max Units

Conditions

30

TMCL MCLR Pulse Width (low)

2

—

—

s (Note 3)

31

TWDT Watchdog Timer Time-out Period

(no postscaler)

2.67

4.0

5.53

ms

32

TOST Oscillator Start-up Timer Period

1024 TOSC — 1024 TOSC — TOSC = OSC1 period

33

TPWRT Power-up Timer Period

—

1.0

—

ms

34

TIOZ I/O High-Impedance from MCLR

Low or Watchdog Timer Reset

—

— 3 TCY + 2 s (Note 1)

36

TIRVST Time for Internal Reference

Voltage to become Stable

—

20

—

s

37

TLVD High/Low-Voltage Detect

Pulse Width

—

200

—

s

38

TCSD CPU Start-up Time

—

200

—

s (Note 2)

Note 1:

2:

3:

The maximum TIOZ is the lesser of (3 TCY + 2 s) or 700 s.

MCLR rising edge to code execution, assuming TPWRT (and TOST, if applicable) has already expired.

The MCLR input has an internal noise filter to avoid nuisance Resets. When deliberately trying to reset the

microcontroller, MCLR must be held low for at least this amount of time to ensure a Reset sequence is

triggered.

 2011 Microchip Technology Inc.

DS39931D-page 513

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