PIC18F44K22T-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F44K22T-I/SO

28/40/44-Pin, Low-Power,High-Performance Microcontrollers with XLP Technology

Microchip Technology 

PIC18(L)F2X/4XK22

TABLE 3-3: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

before Wake-up

Clock Source

after Wake-up

Exit Delay

Clock Ready Status

Bit (OSCCON)

LP, XT, HS

Primary Device Clock

(PRI_IDLE mode)

T1OSC or LFINTOSC(1)

HFINTOSC(2)

None

(Sleep mode)

HSPLL

EC, RC

HFINTOSC(2)

LP, XT, HS

HSPLL

EC, RC

HFINTOSC(1)

LP, XT, HS

HSPLL

EC, RC

HFINTOSC(1)

LP, XT, HS

HSPLL

EC, RC

HFINTOSC(1)

TCSD(1)

TOST(3)

TOST + tPLL(3)

TCSD(1)

TIOBST(4)

TOST(4)

TOST + tPLL(3)

TCSD(1)

None

TOST(3)

TOST + tPLL(3)

TCSD(1)

TIOBST(4)

OSTS

IOSF

OSTS

IOSF

OSTS

IOSF

OSTS

IOSF

Note 1: TCSD is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other

required delays (see Section 3.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.

2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.

3: TOST is the Oscillator Start-up Timer. tPLL is the PLL Lock-out Timer.

4: Execution continues during the HFINTOSC stabilization period, TIOBST.

 2010 Microchip Technology Inc.

Preliminary

DS41412A-page 55

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