PIC18F8722 FAMILY
7.5.4 16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-4 through Figure 7-6. All examples assume
either 20-bit or 21-bit address widths.
FIGURE 7-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD WITH A 1 TCY WAIT STATE
(MICROPROCESSOR MODE)
Apparent Q Q1 Q2 Q3 Q4
Actual Q Q1 Q2 Q3 Q4
Q1 Q2
Q1 Q2
Q3 Q4
Q3 Q4
Q4 Q4 Q4 Q4
Q1 Q2 Q3 Q4
A<19:16>
00h
0Ch
AD<15:0>
3AABh
0E55h
CF33h
9256h
BA0
ALE
OE
WRH ‘1’
WRL ‘1’
CE ‘0’
Memory
Cycle
Instruction
Execution
Opcode Fetch
MOVLW 55h
from 007556h
TBLRD Cycle 1
‘1’
‘1’
‘0’
1 TCY Wait
Table Read
of 92h
from 199E67h
TBLRD Cycle 2
FIGURE 7-5:
EXTERNAL MEMORY BUS TIMING FOR TBLRD
(EXTENDED MICROCONTROLLER MODE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16>
AD<15:0>
CE
ALE
OE
Memory
Cycle
Instruction
Execution
0Ch
CF33h
9256h
Opcode Fetch
TBLRD *
from 000100h
INST(PC – 2)
Opcode Fetch
MOVLW 55h
from 000102h
TBLRD Cycle 1
TBLRD 92h
from 199E67h
TBLRD Cycle 2
Opcode Fetch
ADDLW 55h
from 000104h
MOVLW
DS39646B-page 104
Preliminary
2004 Microchip Technology Inc.