PIC18F8722 FAMILY
FIGURE 1-1:
PIC18F6527/6622/6627/6722 (64-PIN) BLOCK DIAGRAM
Table Pointer<21>
inc/dec logic
21
20
Address Latch
Program Memory
(48/64/96/128
Kbytes)
Data Latch
8
Data Bus<8>
88
PCLATU PCLATH
PCU PCH PCL
Program Counter
31 Level Stack
STKPTR
Table Latch
Data Latch
Data Memory
(3.9 Kbytes)
Address Latch
12
Data Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Access
Bank
12
inc/dec
logic
ROM Latch
Instruction Bus <16>
IR
Address
Decode
OSC1(3)
OSC2(3)
T1OSI
T1OSO
MCLR(2)
VDD, VSS
Instruction
Decode and
Control
State Machine
Control Signals
8
PRODH PRODL
Internal
Oscillator
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
3
BITOP
8
8 x 8 Multiply
8
W
8
8
8
8
ALU<8>
Precision
8
Band Gap
Reference
PORTA
RA0:RA7(1)
PORTB
RB0:RB7(1)
PORTC
RC0:RC7(1)
PORTD
RD0:RD7(1)
PORTE
RE0:RE7(1)
PORTF
RF0:RF7(1)
PORTG
RG0:RG5(1)
BOR
HLVD
ADC
10-bit
Timer0
Timer1 Timer2
Timer3
Timer4 Comparators
ECCP1
ECCP2 ECCP3
CCP4
CCP5 EUSART1 EUSART2 MSSP1 MSSP2
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as
digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.
2004 Microchip Technology Inc.
Preliminary
DS39646B-page 11