PIC18F8722 FAMILY
TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin Buffer
TQFP
Type Type
Description
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
ECCP3
P3A
3
I/O
ST
Digital I/O.
I/O
ST
Enhanced Capture 3 input/Compare 3 output/
PWM 3 output.
O
—
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
TX2
CK2
4
I/O
ST
Digital I/O.
O
—
EUSART2 asynchronous transmit.
I/O
ST
EUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
RX2
DT2
5
I/O
ST
Digital I/O.
I
ST
EUSART2 asynchronous receive.
I/O
ST
EUSART2 synchronous data (see related TX2/CK2).
RG3/CCP4/P3D
RG3
CCP4
P3D
6
I/O
ST
Digital I/O.
I/O
ST
Capture 4 input/Compare 4 output/PWM 4 output.
O
—
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
CCP5
P1D
8
I/O
ST
Digital I/O.
I/O
ST
Capture 5 input/Compare 5 output/PWM 5 output.
O
—
ECCP1 PWM output D.
RG5
See RG5/MCLR/VPP pin.
VSS
9, 25, 41, 56 P
— Ground reference for logic and I/O pins.
VDD
10, 26, 38, 57 P
— Positive supply for logic and I/O pins.
AVSS
20
P
— Ground reference for analog modules.
AVDD
19
P
— Positive supply for analog modules.
Legend:
Note 1:
2:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
P = Power
O
= Output
I2C™ = I2C/SMBus input buffer
Default assignment for ECCP2 when configuration bit CCP2MX is set.
Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared.
DS39646B-page 20
Preliminary
2004 Microchip Technology Inc.