PIC18F8527-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F8527-I
Microchip Technology
PIC18F8527-I Datasheet PDF : 448 Pages
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PIC18F8722 FAMILY
TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin Buffer
TQFP
Type Type
Description
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
I/O
ST
Digital I/O.
O
—
External memory address latch enable.
RJ1/OE
RJ1
OE
61
I/O
ST
Digital I/O.
O
—
External memory output enable.
RJ2/WRL
RJ2
WRL
60
I/O
ST
Digital I/O.
O
—
External memory write low control.
RJ3/WRH
RJ3
WRH
59
I/O
ST
Digital I/O.
O
—
External memory write high control.
RJ4/BA0
RJ4
BA0
39
I/O
ST
Digital I/O.
O
—
External memory byte address 0 control.
RJ5/CE
RJ4
CE
40
I/O
ST
Digital I/O
O
—
External memory chip enable control.
RJ6/LB
RJ6
LB
41
I/O
ST
Digital I/O.
O
—
External memory low byte control.
RJ7/UB
RJ7
UB
42
I/O
ST
Digital I/O.
O
—
External memory high byte control.
VSS
11, 31, 51, 70 P
— Ground reference for logic and I/O pins.
VDD
12, 32, 48, 71 P
— Positive supply for logic and I/O pins.
AVSS
26
P
— Ground reference for analog modules.
AVDD
25
P
— Positive supply for analog modules.
Legend:
Note 1:
2:
3:
4:
5:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
P = Power
O
= Output
I2C™/SMB = I2C/SMBus input buffer
Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except
Microcontroller mode).
Default assignment for ECCP2 in all operating modes (CCP2MX is set).
Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39646B-page 30
Preliminary
2004 Microchip Technology Inc.
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