PIC18F8527-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F8527-I
Microchip Technology
PIC18F8527-I Datasheet PDF : 448 Pages
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PIC18F8722 FAMILY
TABLE 5-3: REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
PORTJ(2)
PORTH(2)
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
ECCP1DEL
TMR4
PR4
T4CON
CCPR4H
CCPR4L
CCP4CON
CCPR5H
CCPR5L
CCP5CON
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
ECCP3AS
ECCP3DEL
ECCP2AS
ECCP2DEL
SSP2BUF
SSP2ADD
RJ7
RJ6
RJ5
RJ4
RJ3
RJ2
RJ1
RJ0
RH7
—
RH6
—
RH5
RG5(5)
RH4
RG4
RH3
RG3
RH2
RG2
RH1
RG1
RH0
RG0
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RA7(4)
RB6
RA6(4)
RB5
RA5
RB4
RA4
RB3
RA3
RB2
RA2
RB1
RA1
RB0
RA0
EUSART1 Baud Rate Generator Register High Byte
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
EUSART2 Baud Rate Generator Register High Byte
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
P1RSEN
P1DC6
P1DC5
P1DC4
P1DC3
P1DC2
P1DC1
P1DC0
Timer4 Register
Timer4 Period Register
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
Capture/Compare/PWM Register 4 High Byte
Capture/Compare/PWM Register 4 Low Byte
—
—
DC4B1
DC4B0
CCP4M3 CCP4M2 CCP4M1 CCP4M0
Capture/Compare/PWM Register 5 High Byte
Capture/Compare/PWM Register 5 Low Byte
—
—
DC5B1
DC5B0
CCP5M3 CCP5M2 CCP5M1 CCP5M0
EUSART2 Baud Rate Generator Register Low Byte
EUSART2 Receive Register
EUSART2 Transmit Register
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0
P3RSEN
P3DC6
P3DC5
P3DC4
P3DC3
P3DC2
P3DC1
P3DC0
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0
P2RSEN
P2DC6
P2DC5
P2DC4
P2DC3
P2DC2
P2DC1
P2DC0
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register in I2C™ Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode.
xxxx xxxx
0000 xxxx
--xx xxxx
x000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
0000 0000
01-0 0-00
0000 0000
01-0 0-00
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0000
60, 156
60, 154
60, 151
60, 149
60, 146
60, 143
60, 140
60, 137
61, 135
61, 252
61, 250
61, 252
61, 250
61, 200
61, 178
61, 178
61, 178
61, 180
61, 180
61, 179
61, 180
61, 180
61, 179
61, 252
61, 260
61, 257
61, 248
61, 249
61, 201
61, 200
61, 201
61, 200
61, 170
61, 170
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 61, 216
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 61, 217
SSP2CON2
GCEN
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN
SEN 0000 0000 61, 218
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, this bit reads as ‘0’.
These registers and/or bits are not implemented on 64-pin devices and are read as ‘0’. Reset values are shown for 80-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as ‘0’.
Bit 7 and Bit 6 are cleared by user software or by a POR.
Bit 21 of TBLPTRU allows access to the device configuration bits.
2004 Microchip Technology Inc.
Preliminary
DS39646B-page 79
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