PIC18F6310/6410/8310/8410
REGISTER 9-12:
IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
U-0
R-0
R-0
U-0
U-0
—
—
RC2IP TX2IP
—
—
bit 7
U-0
R/W-1
—
CCP3IP
bit 0
bit 7-6
bit 5
bit 4
bit 3-1
bit 0
Unimplemented: Read as ‘0’
RC2IP: AUSART Receive Priority Flag bit
1 = High priority
0 = Low priority
TX2IP: AUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
Unimplemented: Read as ‘0’
CCP3IP: CCP3 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39635A-page 114
Preliminary
2004 Microchip Technology Inc.