PIC18LF8410-I/PTQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF8410-I/PTQTP Datasheet PDF : 404 Pages
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PIC18F6310/6410/8310/8410
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Inclusive OR literal with W
IORLW k
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
0000 1001 kkkk kkkk
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed in
W.
1
1
Q2
Read
literal ‘k’
Q3
Process
Data
Q4
Write to W
Example:
IORLW
35h
Before Instruction
W
= 9Ah
After Instruction
W
= BFh
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Inclusive OR W with f
IORWF f {,d {,a}}
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .OR. (f) → dest
N, Z
0001 00da ffff ffff
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT = 13h
W
= 91h
After Instruction
RESULT = 13h
W
= 93h
DS39635A-page 310
Preliminary
2004 Microchip Technology Inc.
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