PIC18F6310/6410/8310/8410
SUBLW
Subtract W from literal
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
SUBLW k
0 ≤ k ≤ 255
k – (W) → W
N, OV, C, DC, Z
0000 1000 kkkk kkkk
W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
1
1
Q2
Read
literal ‘k’
Q3
Process
Data
Q4
Write to W
Example 1:
SUBLW 02h
Before Instruction
W
= 01h
C
=?
After Instruction
W
= 01h
C
= 1 ; result is positive
Z
=0
N
=0
Example 2:
SUBLW 02h
Before Instruction
W
= 02h
C
=?
After Instruction
W
= 00h
C
= 1 ; result is zero
Z
=1
N
=0
Example 3:
SUBLW 02h
Before Instruction
W
= 03h
C
=?
After Instruction
W
= FFh ; (2’s complement)
C
= 0 ; result is negative
Z
=0
N
=1
SUBWF
Subtract W from f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
SUBWF f {,d {,a}}
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – (W) → dest
N, OV, C, DC, Z
0101 11da ffff ffff
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is V, the
result is stored back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is V, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever f ≤ 95
(5Fh). See Section 24.2.3 for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example 1:
SUBWF REG, 1, 0
Before Instruction
REG = 3
W
=2
C
=?
After Instruction
REG = 1
W
=2
C
= 1 ; result is positive
Z
=0
N
=0
Example 2:
SUBWF REG, 0, 0
Before Instruction
REG = 2
W
=2
C
=?
After Instruction
REG = 2
W
=0
C
= 1 ; result is zero
Z
=1
N
=0
Example 3:
SUBWF REG, 1, 0
Before Instruction
REG = 1
W
=2
C
=?
After Instruction
REG = FFh ;(2’s complement)
W
=2
C
= 0 ; result is negative
Z
=0
N
=1
2004 Microchip Technology Inc.
Preliminary
DS39635A-page 323