PIC18LF8410-I/PTQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF8410-I/PTQTP

64/80-Pin Flash Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F6310/6410/8310/8410

TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

before Wake-up

Clock Source

after Wake-up

Exit Delay

Clock Ready Status

bit (OSCCON)

Primary Device Clock

(PRI_IDLE mode)

LP, XT, HS

HSPLL

EC, RC, INTRC(1)

INTOSC(3)

TCSD(2)

OSTS

—

IOFS

T1OSC or INTRC(1)

LP, XT, HS

HSPLL

EC, RC, INTRC(1)

INTOSC(2)

TOST(4)

TOST + trc(4)

TCSD(2)

TIOBST(5)

OSTS

—

IOFS

INTOSC(3)

LP, XT, HS

HSPLL

EC, RC, INTRC(1)

INTOSC(2)

TOST(5)

TOST + trc(4)

TCSD(2)

None

OSTS

—

IOFS

None

(Sleep mode)

LP, XT, HS

HSPLL

EC, RC, INTRC(1)

INTOSC(2)

TOST(4)

TOST + trc(4)

TCSD(2)

TIOBST(5)

OSTS

—

IOFS

Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.

2: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently

with any other required delays (see Section 3.4 “Idle Modes”).

3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.

4: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is

also designated as TPLL.

5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.

 2004 Microchip Technology Inc.

Preliminary

DS39635A-page 47

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