PIC18F6310/6410/8310/8410
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
CCPR1H
CCPR1L
6X10 8X10
6X10 8X10
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
CCP1CON
6X10 8X10
--00 0000
--00 0000
--uu uuuu
CCPR2H
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
6X10 8X10
--00 0000
--00 0000
--uu uuuu
CCPR3H
CCPR3L
CCP3CON
CVRCON
CMCON
6X10
6X10
6X10
6X10
6X10
8X10
8X10
8X10
8X10
8X10
xxxx xxxx
xxxx xxxx
--00 0000
000- 0000
0000 0111
uuuu uuuu
uuuu uuuu
--00 0000
000- 0000
0000 0111
uuuu uuuu
uuuu uuuu
--uu uuuu
uuu- uuuu
uuuu uuuu
TMR3H
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
6X10 8X10
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
6X10 8X10
0000 0000
uuuu uuuu
uuuu uuuu
PSPCON
6X10 8X10
0000 ----
0000 ----
uuuu ----
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
6X10
6X10
6X10
6X10
6X10
8X10
8X10
8X10
8X10
8X10
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
IPR3
PIR3
6X10 8X10
6X10 8X10
--11 ---1
--00 ---0
--11 ---1
--00 ---0
--uu ---u
--uu ---u(1)
PIE3
6X10 8X10
--00 ---0
--00 ---0
--uu ---u
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
6X10
6X10
6X10
6X10
6X10
6X10
8X10
8X10
8X10
8X10
8X10
8X10
11-- 1111
00-- 0000
00-- 0000
1111 1111
0000 0000
0000 0000
11-- 1111
00-- 0000
00-- 0000
1111 1111
0000 0000
0000 0000
uu-- uuuu
uu-- uuuu(1)
uu-- uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu
MEMCON
6X10 8X10
0-00 --00
0-00 --00
u-uu --uu
OSCTUNE
6X10 8X10
00-0 0000
00-0 0000
uu-u uuuu
TRISJ
6X10 8X10
1111 1111
1111 1111
uuuu uuuu
TRISH
6X10 8X10
1111 1111
1111 1111
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
2004 Microchip Technology Inc.
Preliminary
DS39635A-page 59