PIC18F66K22-I/PTRSL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F66K22-I/PTRSL

64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

Microchip Technology 

PIC18F87K22 FAMILY

EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY

BSF

BCF

BSF

BCF

MOVLW

Required MOVWF

Sequence MOVLW

MOVWF

BSF

BSF

BCF

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

INTCON, GIE

0x55

EECON2

0xAA

EECON2

EECON1, WR

INTCON, GIE

EECON1, WREN

; point to Flash program memory

; access Flash program memory

; enable write to memory

; disable interrupts

; write 55h

; write 0AAh

; start program (CPU stall)

; re-enable interrupts

; disable write to memory

7.5.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

7.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. If the write operation is interrupted

by a MCLR Reset or a WDT Time-out Reset during

normal operation, the user can check the WRERR bit

and rewrite the location(s) as needed.

7.5.4

PROTECTION AGAINST

SPURIOUS WRITES

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 28.0 “Special Features of the

CPU” for more details.

7.6 Flash Program Operation During

Code Protection

See Section 28.6 “Program Verification and Code

Protection” for details on code protection of Flash

program memory.

TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TBLPTRU

—

—

bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

TABLAT Program Memory Table Latch

INTCON

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF

INT0IF

RBIF

EECON2 EEPROM Control Register 2 (not a physical register)

EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

WR

RD

IPR6

—

—

—

EEIP

—

CMP3IP CMP2IP CMP1IP

PIR6

—

—

—

EEIF

—

CMP3IF CMP2IF CMP1IF

PIE6

—

—

—

EEIE

—

CMP3IE CMP2IE CMP1IE

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.

DS39960D-page 120

 2009-2011 Microchip Technology Inc.

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