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PIC18F66K22-I/PTRSL View Datasheet(PDF) - Microchip Technology

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Description
Manufacturer
PIC18F66K22-I/PTRSL Datasheet PDF : 550 Pages
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PIC18F87K22 FAMILY
FIGURE 31-8:
PROGRAM MEMORY WRITE TIMING DIAGRAM
OSC1
A<19:16>
BA0
AD<15:0>
ALE
CE
WRH or
WRL
UB or
LB
Q1
Q2
Address
150
151
171
171A
157
Q3
Q4
Address
166
Data
153
156
154
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
Q1
157A
Q2
Address
Address
TABLE 31-12: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ Max Units
150 TadV2alL Address Out Valid to ALE (address setup time)
151 TalL2adl ALE to Address Out Invalid (address hold time)
0.25 TCY – 10 —
5
ns
ns
153 TwrH2adl WRn to Data Out Invalid (data hold time)
5
ns
154 TwrL
WRn Pulse Width
0.5 TCY – 5 0.5 TCY
ns
156 TadV2wrH Data Valid before WRn (data setup time)
0.5 TCY – 10
ns
157 TbsV2wrL Byte Select Valid before WRn 
(byte select setup time)
0.25 TCY
ns
157A TwrH2bsI WRn to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 —
ns
166 TalH2alH ALE to ALE (cycle time)
TCY
ns
171 TalH2csL Chip Enable Active to ALE
0.25 TCY – 20 —
ns
171A TubL2oeH AD Valid to Chip Enable Active
10
ns
DS39960D-page 508
2011 Microchip Technology Inc.

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