PIC18LF4420T-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF4420T-I/SO
Microchip Technology
PIC18LF4420T-I/SO Datasheet PDF : 390 Pages
| |||
PIC18F2420/2520/4420/4520
FIGURE 26-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
bit 6 - - - - - -1
75, 76
SDI
MSb In
bit 6 - - - -1
74
Note: Refer to Figure 26-4 for load conditions.
LSb
LSb In
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
71
TscH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
—
73A Tb2b
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 —
of Byte 2
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
—
75
TdoR
SDO Data Output Rise Time PIC18FXXXX
—
25
PIC18LFXXXX
45
76
TdoF
SDO Data Output Fall Time
—
25
78
TscR
SCK Output Rise Time
(Master mode)
PIC18FXXXX
PIC18LFXXXX
—
25
45
79
TscF
SCK Output Fall Time (Master mode)
—
25
80
TscH2doV, SDO Data Output Valid after PIC18FXXXX
TscL2doV SCK Edge
PIC18LFXXXX
—
50
100
81
TdoV2scH, SDO Data Output Setup to SCK Edge
TdoV2scL
TCY
—
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
DS39631A-page 350
Preliminary
2004 Microchip Technology Inc.
Share Link: 