PIC18F2420/2520/4420/4520
PLL Clock ................................................................. 343
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements ................................................... 345
Timer0 and Timer1 External
Clock Requirements ......................................... 346
USART Synchronous Receive Requirements ......... 357
USART Synchronous Transmission
Requirements ................................................... 357
Top-of-Stack Access .......................................................... 54
TRISE Register
PSPMODE Bit .......................................................... 114
TSTFSZ ............................................................................ 307
Two-Speed Start-up ................................................. 249, 260
Two-Word Instructions
Example Cases .......................................................... 58
TXSTA Register
BRGH Bit ................................................................. 205
V
Voltage Reference Specifications .................................... 338
W
Watchdog Timer (WDT) ........................................... 249, 258
Associated Registers ............................................... 259
Control Register ....................................................... 258
During Oscillator Failure .......................................... 261
Programming Considerations .................................. 258
WCOL ...................................................... 189, 190, 191, 194
WCOL Status Flag ................................... 189, 190, 191, 194
WWW, On-Line Support ...................................................... 6
X
XORLW ............................................................................ 307
XORWF ........................................................................... 308
DS39631A-page 384
Preliminary
2004 Microchip Technology Inc.