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PIC18F258-I/SP View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC18F258-I/SP Datasheet PDF : 402 Pages
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PIC18FXX8
INCFSZ
Increment f, Skip if 0
Syntax:
Operands:
Operation:
Status Affected:
[ label ] INCFSZ f [,d [,a]]
0 f 255
d [0,1]
a [0,1]
(f) + 1 dest,
skip if result = 0
None
Encoding:
Description:
Words:
0011 11da ffff ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE INCFSZ CNT
NZERO :
ZERO :
Before Instruction
PC
=
After Instruction
CNT =
If CNT =
PC
=
If CNT
PC
=
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
INFSNZ
Increment f, Skip if not 0
Syntax:
Operands:
Operation:
Status Affected:
[ label ] INFSNZ f [,d [,a]]
0 f 255
d [0,1]
a [0,1]
(f) + 1 dest,
skip if result 0
None
Encoding:
Description:
Words:
0100 10da ffff ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
ZERO
NZERO
INFSNZ REG
Before Instruction
PC
=
After Instruction
REG =
If REG
PC
=
If REG =
PC
=
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
© 2006 Microchip Technology Inc.
DS41159E-page 303

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