PIC18LF448T-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF448T-I/SP

28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

Microchip Technology 

PIC18FXX8

TABLE 27-20: MASTER SSP I2C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Max Units

Conditions

100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

101 TLOW

Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) —

ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

102 TR

SDA and SCL

Rise Time

100 kHz mode

400 kHz mode

1 MHz mode(1)

—

20 + 0.1 CB

—

1000

300

300

ns CB is specified to be

ns from 10 to 400 pF

ns

103 TF

SDA and SCL

Fall Time

100 kHz mode

400 kHz mode

1 MHz mode(1)

—

20 + 0.1 CB

—

300 ns CB is specified to be

300 ns from 10 to 400 pF

100 ns

90

TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for

Setup Time

400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms Repeated Start

condition

ms

91

THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the

Hold Time

400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms first clock pulse is

ms generated

106 THD:DAT Data Input

Hold Time

100 kHz mode

400 kHz mode

0

—

ns

0

0.9 ms

107 TSU:DAT Data Input

Setup Time

100 kHz mode

400 kHz mode

250

—

ns (Note 2)

100

—

ns

92

TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) —

ms

Setup Time

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

109 TAA

Output Valid

from Clock

100 kHz mode

400 kHz mode

1 MHz mode(1)

—

3500 ns

—

1000 ns

—

—

ns

110 TBUF

Bus Free Time 100 kHz mode

400 kHz mode

4.7

— ms Time the bus must be

1.3

—

ms free before a new

transmission can start

D102 CB

Bus Capacitive Loading

—

400 pF

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the low period of the SCL

signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the

SDA line.

Before the SCL line is released, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode).

DS41159E-page 356

© 2006 Microchip Technology Inc.

Share Link: