PIC18F258-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F258-I/SP

28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module

Microchip Technology 

PIC18FXX8

REGISTER 5-1:

EECON1: EEPROM CONTROL REGISTER 1

R/W-x R/W-x

U-0

R/W-0 R/W-x

EEPGD CFGS

—

FREE WRERR

bit 7

R/W-0

WREN

R/S-0

WR

R/S-0

RD

bit 0

bit 7

EEPGD: Flash Program or Data EEPROM Memory Select bit

1 = Access program Flash memory

0 = Access data EEPROM memory

bit 6

CFGS: Flash Program/Data EE or Configuration Select bit

1 = Access Configuration registers

0 = Access program Flash or data EEPROM memory

bit 5

Unimplemented: Read as ‘0’

bit 4

FREE: Flash Row Erase Enable bit

1 = Erase the program memory row addressed by TBLPTR on the next WR command

(reset by hardware)

0 = Perform write only

bit 3

WRERR: Write Error Flag bit

1 = A write operation is prematurely terminated

(any MCLR or any WDT Reset during self-timed programming in normal operation)

0 = The write operation completed

Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows

tracing of the error condition.

bit 2

WREN: Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the EEPROM or Flash memory

bit 1

WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

0 = Write cycle is complete

bit 0

RD: Read Control bit

1 = Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

S = Settable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

DS41159E-page 60

© 2006 Microchip Technology Inc.

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