PIC32MX120F032B-50I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX120F032B-50I/SP

32-bit Microcontrollers (up to 256 KB Flash and 64 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX

16.0 SERIAL PERIPHERAL

INTERFACE (SPI)

Note 1: This data sheet summarizes the

features of the PIC32MX1XX/2XX family

of devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 23. “Serial

Peripheral

Interface

(SPI)”

(DS60001106) in the “PIC32 Family

Reference Manual”, which is available

from the Microchip web site

(www.microchip.com/PIC32).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The SPI module is a synchronous serial interface that

is useful for communicating with external peripherals

and other microcontrollers. These peripheral devices

may be Serial EEPROMs, Shift registers, display driv-

ers, Analog-to-Digital Converters (ADC), etc. The

PIC32 SPI module is compatible with Motorola® SPI

and SIOP interfaces.

Some of the key features of the SPI module are:

• Master mode and Slave mode support

• Four clock formats

• Enhanced Framed SPI protocol support

• User-configurable 8-bit, 16-bit and 32-bit data width

• Separate SPI FIFO buffers for receive and transmit

- FIFO buffers act as 4/8/16-level deep FIFOs

based on 32/16/8-bit data width

• Programmable interrupt event on every 8-bit,

16-bit and 32-bit data transfer

• Operation during Sleep and Idle modes

• Audio Codec Support:

- I2S protocol

- Left-justified

- Right-justified

- PCM

FIGURE 16-1:

SPI MODULE BLOCK DIAGRAM

Internal

Data Bus

Read

SPIxBUF

Write

SPIxRXB FIFO SPIxTXB FIFO

FIFOs Share Address SPIxBUF

Transmit

SDIx

Receive

SPIxSR

bit 0

SDOx

SSx/FSYNC

Slave Select

and Frame

Sync Control

Shift

Control

Clock

Control

Edge

Select

SCKx

Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.

MCLKSEL

1

Baud Rate

Generator

0

MSTEN

REFCLK

PBCLK

© 2011-2014 Microchip Technology Inc.

DS60001168F-page 165

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