PIC32MX1XX/2XX
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
Tantalum or
VDD ceramic 10 µF
ESR ≤ 3Ω(3)
R
R1
MCLR
0.1 µF
Ceramic
C
VSS
VDD
0.1 µF
Ceramic
Connect(2)
L1(2)
PIC32
VUSB3V3(1)
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
Note 1:
2:
If the USB module is not used, this pin must be
connected to VDD.
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1Ω and the inductor
capacity greater than 10 mA.
Where:
f
=
F-----C---N----V-
2
(i.e., ADC conversion rate/2)
f = -----------1------------
(2π LC)
L
=
⎛
⎝
(---2---π----f1------C-----)⎠⎞
2
3: Aluminum or electrolytic capacitors should not be
used. ESR ≤ 3W from -40ºC to 125ºC @ SYSCLK
frequency (i.e., MIPS).
2.2.1 BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3 Capacitor on Internal Voltage
Regulator (VCAP)
2.3.1 INTERNAL REGULATOR MODE
A low-ESR (1 Ohm) capacitor is required on the VCAP
pin, which is used to stabilize the internal voltage regu-
lator output. The VCAP pin must not be connected to
VDD, and must have a CEFC capacitor, with at least a
6V rating, connected to ground. The type can be
ceramic or tantalum. Refer to Section 29.0 “Electrical
Characteristics” for additional information on CEFC
specifications.
2.4 Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device programming and debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
VDD
MCLR PIN CONNECTIONS
R 10k R1(1)
0.1 µF(2)
C 1 kΩ
1
5
4
2
3
6
VDD
VSS
NC
MCLR
PIC32
PGECx(3)
PGEDx(3)
Note 1:
2:
3:
470Ω ≤ R1 ≤ 1Ω will limit any current flowing into
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
interfering with the Debug/Programmer tools.
The capacitor can be sized to prevent unintentional
Resets from brief glitches or to extend the device
Reset period during POR.
No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
DS60001168F-page 28
© 2011-2014 Microchip Technology Inc.