PIC32MX230F064C-50I View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F064C-50I

32-bit Microcontrollers (up to 256 KB Flash and 64 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX

Coprocessor 0 also contains the logic for identifying

and managing exceptions. Exceptions can be caused

by a variety of sources, including alignment errors in

data, external events or program errors. Table 3-3 lists

the exception types in order of priority.

TABLE 3-3:

Exception

Reset

DSS

DINT

NMI

Interrupt

DIB

AdEL

IBE

DBp

Sys

Bp

RI

CpU

CEU

Ov

Tr

DDBL/DDBS

AdEL

AdES

DBE

DDBL

MIPS32® M4K® PROCESSOR CORE EXCEPTION TYPES

Description

Assertion MCLR or a Power-on Reset (POR).

EJTAG debug single step.

EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the

EjtagBrk bit in the ECR register.

Assertion of NMI signal.

Assertion of unmasked hardware or software interrupt signal.

EJTAG debug hardware instruction break matched.

Fetch address alignment error.

Fetch reference to protected address.

Instruction fetch bus error.

EJTAG breakpoint (execution of SDBBP instruction).

Execution of SYSCALL instruction.

Execution of BREAK instruction.

Execution of a reserved instruction.

Execution of a coprocessor instruction for a coprocessor that is not enabled.

Execution of a CorExtend instruction when CorExtend is not enabled.

Execution of an arithmetic instruction that overflowed.

Execution of a trap (when trap condition is true).

EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).

Load address alignment error.

Load reference to protected address.

Store address alignment error.

Store to protected address.

Load or store bus error.

EJTAG data hardware breakpoint matched in load data compare.

3.3 Power Management

The MIPS M4K processor core offers many power man-

agement features, including low-power design, active

power management and power-down modes of opera-

tion. The core is a static design that supports slowing or

Halting the clocks, which reduces system power con-

sumption during Idle periods.

3.3.1

INSTRUCTION-CONTROLLED

POWER MANAGEMENT

The mechanism for invoking Power-Down mode is

through execution of the WAIT instruction. For more

information on power management, see Section 25.0

“Power-Saving Features”.

3.4 EJTAG Debug Support

The MIPS M4K processor core provides an Enhanced

JTAG (EJTAG) interface for use in the software debug

of application and kernel code. In addition to standard

User mode and Kernel modes of operation, the M4K

core provides a Debug mode that is entered after a

debug exception (derived from a hardware breakpoint,

single-step exception, etc.) is taken and continues until

a Debug Exception Return (DERET) instruction is

executed. During this time, the processor executes the

debug exception handler routine.

The EJTAG interface operates through the Test Access

Port (TAP), a serial communication port used for trans-

ferring test data in and out of the core. In addition to the

standard JTAG instructions, special instructions

defined in the EJTAG specification define which

registers are selected and how they are used.

DS60001168F-page 34

© 2011-2014 Microchip Technology Inc.

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