ZPSD211RM View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD211RM Datasheet PDF : 51 Pages
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14.0
System
Applications
PSD211R Family
In Figure 11, the PSD211R is configured to interface with Intel’s 80C31, which is a 16-bit
address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order
address byte. The 80C31 uses signals RD to read from data memory and PSEN to read
from code memory. It uses WR to write into the data memory. It also uses active high reset
and ALE signals. Only the necessary connections are shown.
Figure 11. Interface With Intel’s 80C31
Reset
MICROCONTROLLER
31 EA/VP
19 X1
18 X2
P0.0 39
P0.1 38
P0.2 37
P0.3 36
P0.4 35
P0.5 34
P0.6 33
P0.7 32
9 RESET
12
13
INT0
INT1
14 T0
15 T1
1 P1.0
2 P1.1
3 P1.2
4 P1.3
5 P1.4
6 P1.5
7 P1.6
8 P1.7
P2.0 21
P2.1 22
P2.2 23
P2.3 24
P2.4 25
P2.5 26
P2.6 27
P2.7 28
RD 17
WR 16
PSEN 29
ALE 30
TXD 11
RXD 10
80C31
VCC
44
23
24
25
26
27
28
29
30
AD0/A0
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
31
32
33
35
AD8/A8
AD9/A9
AD10/A10
AD11/A11
36 AD12/A12
37 AD13/A13
38 AD14/A14
39 AD15/A15
22 RD
2
1
13
3
WR/VPP
PSEN
ALE
RESET
PSD211R
0.1µF
PA0 21
PA1 20
PA2 19
PA3 18
PA4 17
PA5 16
PA6 15
PA7 14
PB0 11
PB1 10
PB2 9
PB3 8
PB4 7
PB5 6
PB6 5
PB7 4
PC0 40
PC1 41
PC2 42
A19/CSI 43
GND
34 12
NOTE: RESET to the PSD211R must be the output of a RESET chip or buffer.
If RESET to the 80C31 is the output of an RC circuit, a separate buffered RC RESET to the
PSD211R (shorter than the 80C31 RC RESET) must be provided to avoid a race condition.
21
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