PSD4114F3V View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD4114F3V

Flash In-System-Programmable Peripherals for 16-Bit MCUs

STMicroelectronics 

Preliminary Information

PSD4000 Series

The

PSD4000

Functional

Blocks

(cont.)

9.1.4 Page Register

The eight bit Page Register increases the addressing capability of the microcontroller by a

factor of up to 256. The contents of the register can also be read by the microcontroller.

The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD decoder and

can be included in the Flash Memory, secondary Flash memory, and SRAM chip select

equations.

If memory paging is not needed, or if not all 8 page register bits are needed for memory

paging, then these bits may be used in the PLD for general logic. See Application

Notes.

Figure 8 shows the Page Register. The eight flip flops in the register are connected to the

internal data bus. The microcontroller can write to or read from the Page Register. The

Page Register can be accessed at address location CSIOP + E0h.

Figure 8. Page Register

RESET

D0

Q0

D1

Q1

DATA BUS D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

R/W

D7

Q7

PAGE

REGISTER

PGR0

PGR1

PGR2

PGR3

PGR4

PGR5

PGR6

PGR7

DPLD

AND

GPLD

FLASH

PLD

INTERNAL

SELECTS

AND LOGIC

29

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