PSD511B1-C-90UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD511B1-C-90UI Datasheet PDF : 153 Pages
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PSD5XX Family
13.11 Microcontroller Interface –AC/DC Parameters
(ZPSD5XXV Versions)
Explanation of AC Symbols for Non ZPLD Timing.
Example:
t AVLX Time from Address Valid to ALE Invalid.
A – Address
C – Power Down
D– Input Data
E– E
H – Logic Level High
I – Interrupt
L – Logic Level Low or ALE
N – Reset
P – Port Signal
Q – Output Data
R – WR, UDS, LDS, DS, IORD, PSEN
S – Chip Select
T – R/W
t – Time
V – Valid
X – No Longer a Valid Logic Level
Z – Float
Read Timing (3.0 V ± 10%)
Symbol
Parameter
Conditions
-20
-25 EPROM_CMiser
Min Max Min Max
ON
Unit
t LVLX
t AVLX
t LXAX
t AVQV
t SLQV
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Data Valid
CS Valid to Data Valid
RD to Data Valid 8/16-Bit Bus
(Note 4)
(Note 4)
(Note 4)
(Note 1)
30
30
0
ns
12
15
0
ns
12
17
0
ns
200
250
Add 20
ns
200
275
Add 20
ns
50
80
0
ns
RD to Data Valid 8-Bit Bus,
t RLQV 8031 Separate Mode
(Note 2)
57
90
0
ns
RD to Data Valid from Interrupt Controller (Note 3)
50
90
0
ns
t RHQX RD Data Hold Time
(Note 1)
0
0
0
ns
tRLRH RD Pulse Width
(Note 1)
40
70
0
ns
tRHQZ RD to Data High-Z
(Note 1)
45
45
0
ns
tEHEL E Pulse Width
40
70
0
ns
tTHEH R/W Setup Time to Enable
20
22
0
ns
tELTL R/W Hold Time After Enable
0
0
0
ns
t AVPV
Address Input Valid to
Address Output Delay
In 16-Bit Data Bus
Mode (Note 5)
40
In 8-Bit Data Bus
Mode (Note 5)
50
60
0
ns
60
0
ns
NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals (in 8031 combined mode).
2. RD and PSEN have the same timing for 8031 separate mode.
3. Read to Data Valid of the Interrupt Request Latch and Interrupt Priority Status. RD timing has the same timing as PSEN, DS, LDS,
UDS signals.
4. Any input used to select an internal ZPSD5XX function.
5. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
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