ST92P141K4D0 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92P141K4D0

8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL

STMicroelectronics 

ST92141 - EXTENDED FUNCTION TIMER (EFT)

EXTENDED FUNCTION TIMER (Cont’d)

7.3.3.5 Forced Compare Mode

In this section i may represent 1 or 2.

The following bits of the CR1 register are used:

FOLV2 FOLV1 OLVL2

OLVL1

When the FOLVi bit is set, the OLVLi bit is copied

to the OCMPi pin. The OLVLi bit has to be toggled

in order to toggle the OCMPi pin when it is enabled

(OCiE bit=1).

The OCFi bit is not set, and thus no interrupt re-

quest is generated.

7.3.3.6 One Pulse Mode

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

Procedure

To use one pulse mode, select the following in the

the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit.

And select the following in the CR2 register:

– Set the OC1E bit, the OCMP1 pin is then dedi-

cated to the Output Compare 1 function.

– Set the OPM bit.

– Select the timer clock CC[1:0] (see Table 22

Clock Control Bits).

Figure 61. One Pulse Mode Timing

Load the OC1R register with the value corre-

sponding to the length of the pulse (see the formu-

la in Section 7.3.3.7).

One pulse mode cycle

When

event occurs

on ICAP1

Counter is

initialized

to FFFCh

When

Counter

= OC1R

OCMP1 = OLVL2

OCMP1 = OLVL1

Then, on a valid event on the ICAP1 pin, the coun-

ter is initialized to FFFCh and OLVL2 bit is loaded

on the OCMP1 pin. When the value of the counter

is equal to the value of the contents of the OC1R

register, the OLVL1 bit is output on the OCMP1

pin, (See Figure 61).

Note: The OCF1 bit cannot be set by hardware in

one pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

The ICF1 bit is set when an active edge occurs

and can generate an interrupt if the ICIE bit is set.

When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

COUNTER .... FFFC FFFD FFFE

ICAP1

2ED0 2ED1 2ED2

2ED3

FFFC FFFD

OCMP1

OLVL2

OLVL1

compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

OLVL2

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