ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont’d)
OUTPUT PERIPHERAL REGISTER (OPR)
R252 - Read/Write
Register Page: 48
Reset Value: 0000 0000 (00h)
INTERRUPT MASK REGISTER (IMR)
R253 - Read/Write
Register Page: 48
Reset Value: 0000 0000 (00h)
7
0
7
0
OPE ODS UH UL VH VL WH WL
CM0E CPTE OTCE ADTE ZPCE CPUE CPVE CPWE
Bit 7 = OPE: Output Port Enable.
This bit can be set by software only if the NMI bit is
cleared.
0: Output port is in high impedance (without pull-
up and pull-down resistor).
1: Output port is available for data transfer.
Bit 6 = ODS: Output Data Selection.
0: Dead time generator data.
1: Select the Bit 5:0 data
Bit 5:0 = Uh, Ul, Vh, Vl, Wh, Wl phases
These bits can be sent out through the output port.
Bit 7 = CM0E: Compare 0 of PWM counter enable.
0: Disabled.
1: Enabled.
Bit 6 = CPTE: Capture of Tacho counter Interrupt
enable.
0: Disabled.
1: Enabled.
Bit 5 = OTCE: Overflow of Tacho counter Interrupt
enable.
0: Disabled.
1: Enabled.
Bit 4 = ADTE: Automatic data transfer Interrupt
enable.
0: Disabled.
1: Enabled.
Bit 3 = ZPCE: Zero of PWM counter interrupt ena-
ble.
0: Disabled.
1: Enabled.
Bit 2:0 = CPUE, CPVE, CPWE: Compare U, V, W
interrupt enable.
0: Disabled.
1: Enabled.
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