ST92P141K4D0 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST92P141K4D0 Datasheet PDF : 179 Pages
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ST92141 - ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
COMPARE RESULT REGISTER (CRR)
R252 - Read/Write
Register Page: 63
Reset Value: 0000 1111 (0Fh)
7
0
C7U C6U C7L C6L X PR2 PR1 PR0
The result of the comparison between the current
value of data registers 6 and 7 and the threshold
registers is stored in the 4 most significant bits of
this register.
Bit 7 = C7U: Compare Reg 7 Upper threshold
Set when converted data is greater than or equal
to the threshold value. Not affected otherwise.
Bit 6 = C6U: Compare Reg 6 Upper threshold
Set when converted data is greater than or equal
to the threshold value. Not affected otherwise.
Bit 5 = C7L: Compare Reg 7 Lower threshold
Set when converted data is less than the threshold
value. Not affected otherwise.
Bit 4 = C6L: Compare Reg 6 Lower threshold
Set when converted data is less than the threshold
value. Not affected otherwise.
These bits should be reset at the end of the “Out of
Range” interrupt service routine.
Note: Any software reset request of the ICR, will
also cause all the compare status bits to forced by
hardware to zero, in order to prevent possible
overwriting if an interrupt request occurs between
reset and the Interrupt request software reset.
Bit 3 = undefined, return '1' when red.
Bit 2:0 = PR[2:0]: Clock divider bits
These bits enable a frequency division factor de-
pending on the value stored:
Table 30. Frequency Division Factors
PR[2:0]
bits
Freq. Div.
Factor
(FDF)
Max. con-
version
time
(INTCLK)
Min. sam-
pling time
(INTCLK)
111
1
138
84
110
4
552
336
101
6
828
504
100
8
1104
672
011
10
1380
840
010
12
1656
1008
001
14
1932
1176
000
16
2208
1344
Warning: If the prescaler programming value is
changed during a conversion, the user has to re-
start the conversion (i.e. simply rewriting the CLR
register with the same value).
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