ST92141 - INTERRUPTS
EXTERNAL INTERRUPTS (Cont’d)
Figure 22. External Interrupts Control Bits and Vectors
n
Watchdog/Timer IA0S
End of count
TEA0
“0”
VECTOR V7 V6 V5 V4 0 0 0 0
Priority level PL2A PL1A 0
INT 0 pin
“1”
*
INTS
Mask bit IMA0
Pending bit IPA0
STIM Interrupt
“0”
VECTOR V7 V6 V5 V4 0 0 1 0
Priority level PL2A PL1A 1
not connected
“1”
EFTIS
Mask bit IMA1
Pending bit IPA1
EFT Interrupt
“1”
VECTOR V7 V6 V5 V4 0 1 0 0
Priority level PL2B PL1B 0
not connected
“0”
Mask bit IMB0
Pending bit IPB0
INT A0
request
INT A1
request
INT B0
request
not connected
VECTOR V7 V6 V5 V4 0 1 1 0
Priority level PL2B PL1B 1
Mask bit IMB1
Pending bit IPB1
INT B1
request
not connected
SPIS
SPI Interrupt
“1”
INT 6 pin
not connected
“0”
RCCU interrupt INT_SEL
TED0
“1”
“0” *
ID1S
WUIMU interrupt
“1”
not connected
“0”
* Shared channels, see warning
n
VECTOR V7 V6 V5 V4 1 0 0 0
Priority level PL2C PL1C 0
Mask bit IMC0
Pending bit IPC0
INT C0
request
VECTOR V7 V6 V5 V4 1 0 1 0
Priority level PL2C PL1C 1
Mask bit IMC1
Pending bit IPC1
INT C1
request
VECTOR V7 V6 V5 V4 1 1 0 0
Priority level PL2D PL1D 0
Mask bit IMD0
Pending bit IPD0
INT D0
request
VECTOR V7 V6 V5 V4 1 1 1 0
Priority level PL2D PL1D 1
Mask bit IMD1
Pending bit IPD1
INT D1
request
47/179
1