ST92163R4D1L View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92163R4D1L

8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT

STMicroelectronics 

ST92163 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

DMA TRANSACTIONS (Cont’d)

When selecting the DMA transaction with memory,

bit DCPR.RM (bit 0 of DCPR) must be cleared.

To select between using the ISR or the DMASR reg-

ister to extend the address, (see Memory Manage-

ment Unit chapter), the control bit DAPR.PS (bit 0

of DAPR) must be cleared or set respectively.

The DMA transaction Counter must be initialized

with the number of transactions to perform and will

be decremented after each transaction. The DMA

Address must be initialized with the starting ad-

dress of the DMA table and is increased after each

transaction. These two registers must be located

between addresses 00h and DFh of the Register

File.

Once a DMA channel is initialized, a transfer can

start. The direction of the transfer is automatically

defined by the type of peripheral and programming

mode.

Once the DMA table is completed (the transaction

counter reaches 0 value), an Interrupt request to

the CPU is generated.

When the Interrupt Pending (IP) bit is set by a

hardware event (or by software), and the DMA

Mask bit (DM) is set, a DMA request is generated.

If the Priority Level of the DMA source is higher

than, or equal to, the Current Priority Level (CPL),

the DMA transfer is executed at the end of the cur-

rent instruction. DMA transfers read/write data

from/to the location pointed to by the DMA Ad-

dress Register, the DMA Address register is incre-

mented and the Transaction Counter Register is

decremented. When the contents of the Transac-

tion Counter are decremented to zero, the DMA

Mask bit (DM) is cleared and an interrupt request

is generated, according to the Interrupt Mask bit

(End of Block interrupt). This End-of-Block inter-

rupt request is taken into account, depending on

the PRL value.

WARNING. DMA requests are not acknowledged

if the top level interrupt service is in progress.

Figure 33. DMA Between Memory and Peripheral

IDCR

IVR

DAPR

DCPR

DATA

PERIPHERAL

PAGED REGISTERS

DMA TRANSACTION

FF h

PAGED

REGISTERS

F0h

EFh

SYSTEM

REGISTERS

E0h

DFh

DATA

ALREADY

TRANSFERRED

DMA

TABLE

n

72/224

DMA

TRANSACTION

COUNTER

DMA

ADDRESS

REGISTER FILE

END OF BLOCK

INTERRUPT

SERVICE ROUTINE

0100h

0000h

ISR ADDRESS

MEMORY

VECTO R

TABLE

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