ST92163R4D1L View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST92163R4D1L
STMicroelectronics
ST92163R4D1L Datasheet PDF : 224 Pages
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ST92163 - RESET AND CLOCK CONTROL UNIT (RCCU)
PLL CONFIGURATION REGISTER (PLLCONF)
R246 - Read/Write
Register Page: 55
Reset Value: xx00 x111
7
0
-
- MX1 MX0 - DX2 DX1 DX0
Bit 7:6 = Reserved.
Bit 5:4 = MX[1:0]: PLL Multiplication Factor.
Refer to Table 14 for multiplier settings.
Bit 3 = Reserved.
Bit 2:0 = DX[2:0]: PLL output clock divider factor.
Refer to Table 15 for divider settings.
Table 14. PLL Multiplication Factors
MX1
1
0
1
0
MX0
0
0
1
1
CLOCK2 x
14
10
8
6
Table 15. Divider Configuration
DX2 DX1 DX0
CK
0
0
0
PLL CLOCK/1
0
0
1
PLL CLOCK/2
0
1
0
PLL CLOCK/3
0
1
1
PLL CLOCK/4
1
0
0
PLL CLOCK/5
1
0
1
PLL CLOCK/6
1
1
0
PLL CLOCK/7
1
1
1
CLOCK2
(PLL OFF, Reset State)
Figure 39. RCCU General Timing
PLL turned on by user
PLL selected by user
STOP
pin
External
RESET
Xt al
clock
Multiplier
clock
Internal
reset
INTCLK
Xtal/2 PLL
Xtal/2 PLL
(*) if DIV2 =1
(**) +/- 1 TXtal
((N-1)*512+510)xT Xtal(**)
PLL
Lock-in
4 xTsys
time
510 x TXtal(*) PLL
Lock-in
Quartz
tim e
start-up
Exit from RESET
STOP
Acknowledged
Switch to
PLL clock
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