PSD811G3V-B-20UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD811G3V-B-20UI Datasheet PDF : 110 Pages
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PSD835G2
The
PSD4000
Functional
Blocks
(cont.)
PSD8XX Family
9.4.8 Port F – Functionality and Structure
Port F can be configured to perform one or more of the following functions:
t MCU I/O Mode
t CPLD Output – external chip select ECS[7:0] can be connected to Port F (or Port C).
t CPLD Input – as direct input ot the CPLD array.
t Address In – additional high address inputs. Direct input to the CPLD array, no Input
Micro⇔Cells latching is available.
t Latched Address Out – Provide latched address out per Table 29.
t Slew Rate – pins can be set up for fast slew rate.
t Data Port – connected to D[7:0] when Port F is configured as Data Port for a
non-multiplexed bus.
t Peripheral I/O Mode
9.4.9 Port G – Functionality and Structure
Port G can be configured to perform one or more of the following functions:
t MCU I/O Mode
t Latched Address Out – provide latched address out per Table 29.
t Open Drain – pins can be configured in Open Drain Mode
Figure 28. Ports E, F and G Structure
WR
ADDRESS
ALE
DATA OUT
REG.
DQ
DQ
G
EXT. CS (PORT F)
READ MUX
P
D
B
DATA OUT
ADDRESS
A[ 7:0] OR A[15:8]
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
PORT PIN
CONTROL REG.
DQ
WR
DIR REG.
DQ
WR
ENABLE PRODUCT TERM (.OE)
ENABLE OUT
CPLD INPUT (PORT F)
ISP OR BATTERY BACK-UP (PORT E)
CONFIGURATION
BIT
63
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