PSD811G3V-C-12MI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD811G3V-C-12MI Datasheet PDF : 110 Pages
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PSD835G2
PSD8XX Family
PSD835G2 AC/DC Parameters – GPLD Timing Parameters
(5 V ± 10% Versions)
GPLD Micro⇔Cell Asynchronous Clock Mode Timing (5 V ± 10% Versions)
Symbol
Parameter
Conditions
-70
-90
PT TURBO Slew
Min Max Min Max Aloc OFF Rate Unit
Maximum Frequency
External Feedback
1/(tSA+ t CO A)
38.4
26.32
MHz
fMAXA
Maximum Frequency
Internal Feedback
( fCNTA)
Maximum Frequency
Pipelined Data
1/(tSA+ t CO A–10)
1/(tCH A+ t CLA)
62.5
47.6
35.71
37.03
MHz
MHz
t SA
Input Setup Time
6
8
Add 2 Add 12
ns
t HA
Input Hold Time
7
12
ns
tCHA Clock Input High Time
9
12
Add 12
ns
tCLA Clock Input Low Time
12
15
Add 12
ns
tCOA Clock to Output Delay
21
30
Add 12 Sub 2 ns
tARDA GPLD Array Delay
Any Micro⇔Cell
11
16 Add 2
ns
tMINA Minimum Clock Period 1/ fCNTA
16
28
ns
Input Micro⇔Cell Timing (5 V ± 10% Versions)
Symbol
Parameter
Conditions
-70
-90
Min Max Min Max
PT TURBO
Aloc OFF Unit
tIS
Input Setup Time
tIH
Input Hold Time
tINH NIB Input High Time
t IN L
NIB Input Low Time
tINO NIB Input to Combinatorial Delay
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
0
0
ns
15
20
Add 12 ns
9
12
ns
9
12
ns
34
46 Add 2 Add 12 ns
NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
79
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