PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Figure 50. ISC Timing
TCK
tISCCH
t ISCCL
t ISCPSU tISCPH
TDI/TMS
t ISCPZV
t ISCPCO
ISC OUTPUTS/TDO
tISCPVZ
ISC OUTPUTS/TDO
AI02865
Table 69. ISC Timing (5V devices)
Symbol
Parameter
Conditions
tISCCF
Clock (TCK, PC1) Frequency (except for
PLD)
(Note 1)
tISCCH
Clock (TCK, PC1) High Time (except for
PLD)
(Note 1)
tISCCL
Clock (TCK, PC1) Low Time (except for
PLD)
(Note 1)
tISCCFP Clock (TCK, PC1) Frequency (PLD only)
(Note 2)
tISCCHP Clock (TCK, PC1) High Time (PLD only)
(Note 2)
tISCCLP Clock (TCK, PC1) Low Time (PLD only)
(Note 2)
tISCPSU ISC Port Set Up Time
tISCPH ISC Port Hold Up Time
tISCPCO ISC Port Clock to Output
tISCPZV ISC Port High-Impedance to Valid Output
tISCPVZ
ISC Port Valid Output to
High-Impedance
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
-70
-90
-15
Unit
Min Max Min Max Min Max
20
18
14 MHz
23
26
31
ns
23
26
31
ns
2
2
2 MHz
240
240
240
ns
240
240
240
ns
7
8
10
ns
5
5
5
ns
21
23
25 ns
21
23
25 ns
21
23
25 ns
98/110